Systems that do not transmit a clock signal with the data must manufacture a properly synchronized clock from the data to accurately recover data bits from the incoming data stream. Accurate data recovery requires clock generation circuitry in these systems to have low jitter and low phase error relative to the data stream. Phase error greater than 0.5 unit intervals (U.I.), or 500 ps for a 1 Gbps system, causes erroneous data recovery.
Two conventional systems attempt to combat the phase error problem. Ewen et al., "Single-Chip 1062 Mbaud CMOS Transceiver for Serial Data Communication," 1995 International Solid-State Circuits Conference, Digest of Technical Papers, pp. 32-33, describes one system, and Yang et al., "A 0.8 um CMOS 2.5 Gb/s Oversampled Receiver for Serial Links," 1996 International Solid State Circuits Conference, Digest of Technical Papers, pp. 200-201, describes the other.
The first conventional system uses a clock recovery circuit to obtain low phase error. A phase or phase/frequency locked loop determines the underlying clock period in the incoming data stream, and through careful design of the loop's frequency transfer function controls the phase error. Limits in the loop's frequency transfer function due to instability concerns, however, hamper the first system's success in completely eliminating the phase error.
The second conventional system uses a clock generation circuit to obtain low phase error. The clock generation circuit uses a local clock, close in frequency to a harmonic of the incoming data's frequency, to generate a clock signal. Because the local clock is not synchronous to the incoming data, the second system oversamples (typically by 3.times.) the data, and a decision circuit chooses the appropriate sample.
The second system tries to control phase error through the decision circuit's tracking of phase shifts between the local clock and the data stream. Because the decision circuit can only choose from among available samples, and the actual correct sampling point may lie between two of the samples taken, this system suffers severe limitations. For 3.times. oversampling, this possibly introduces up to 0.16 U.I. of phase error, a value that requires higher sampling rates to reduce. Higher sampling rates may not be feasible, however, due to area, power, and bandwidth concerns. Additionally, the digital phase tracking mechanism has a low bandwidth, thus causing situations where the phase error may be greater than 0.5 U.I.
In both of the conventional systems described above, the phase error remains large enough to be a significant component of the overall data bit recovery error rate due to the systems' inability to sufficiently align the generated clock to the data stream. Therefore, a need exists to reduce this phase error.